View MAX8973A_9071058.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX8973A high-effciency, three-phase, dc-dc step-down switching regulator delivers up to 9a of output current in a compact footprint with excellent transient response. each phase operates at a 2mhz fxed frequency, allowing the use of small magnetic components. maxim integrateds proprietary rotational phase spreading algorithm optimizes effciency at low output currents. software-selectable forced-pwm mode allows either fxed-frequency operation, or improved effciency at light load with a variable frequency in skip mode. the triple- inductor architecture reduces the size of the external components while providing the beneft of ripple current cancellation. the MAX8973A operates from a 2.6v to 4.5v input voltage range. an i 2 c 3.0-compatible serial interface, supporting clock rates up to 3.4mhz, controls key regulator parameters such as output voltage, output slew rate, and on/off control. output voltage is programmable from 0.60625v to 1.4v in 6.25mv increments. the default output voltage is factory programmable. an en input enables and disables the output, while a dvs pin selects two different output voltages without relying on the serial interface. fully differential remote sense ensures precise dc regulation at the point of load. total output error is less than 0.8% over, line, and temperature at 1.2v output. output ripple is typically < 1% of the output voltage setting when the processor is in the idle state (light loads) and < 0.5% at medium and high loads. other features include internal soft-start control circuitry to reduce inrush current, guaranteed monotonic voltage adjustment, over-current protection, and over-temperature protection. the MAX8973A operates over the -40c to +85c extended temperature range and is packaged in an ultra-small wlp package. features up to 9a output current > 91% peak efficiency at 3.6v in , 1.2v out rotational phase spreading maximizes efficiency at light loads initial accuracy of 0.5% at 1.2v output 0.8% output accuracy over line and temperature at 1.2v output enhanced t ransient response minimizes output droop with large load steps soft-stop recovers output capacitor charge when converter is disabled programmable v out : 0.60625v to 1.4v (6.25mv step size) powers up into prebiased output 3.4mhz i 2 c 3.0-compatible serial interface fixed 2mhz pwm switching frequency per phase small (< 1h) inductor for each phase overcurrent, short-circuit, and thermal protection applications smartphones tablets ultrabooks 19-6587; rev 0; 2/13 ordering information and typical operating circuit appear at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max8973.related . evaluation kit available MAX8973A 9a, three-phase step-down switching regulator
maxim integrated 2 table of contents general description ............................................................................ 1 features ..................................................................................... 1 applications .................................................................................. 1 absolute maximum ratings ...................................................................... 5 package thermal characteristics ................................................................. 5 electrical characteristics ........................................................................ 5 typical operating characteristics ................................................................ 18 pin configuration ............................................................................. 25 pin description ............................................................................... 25 detailed description ........................................................................... 27 enabling the regulator ....................................................................... 29 startup delay (biasen) ................................................................... 29 startup ramp rate ....................................................................... 29 disabling the regulator (active discharge) ....................................................... 29 soft-stop (active energy recovery) .......................................................... 30 resistive discharge ....................................................................... 30 setting the output voltage .................................................................... 30 dvs ................................................................................... 30 default power-up voltage .................................................................. 30 slew rate control ........................................................................ 31 control scheme ............................................................................ 31 modes of operation (skip, mid, ccm) ......................................................... 31 modes of operation (fpwm) ................................................................ 31 current sensing .......................................................................... 31 maximum output current .................................................................. 32 overload and short circuit protection ......................................................... 32 enhanced transient response (etr) ........................................................... 32 remote sense .............................................................................. 32 thermal protection .......................................................................... 32 i 2 c interface ............................................................................... 32 i 2 c interface features ..................................................................... 32 i 2 c system configuration .................................................................. 33 i 2 c interface power ....................................................................... 33 i 2 c data transfer ......................................................................... 33 i 2 c start and stop conditions ............................................................... 33 i 2 c acknowledge bit ...................................................................... 33 i 2 c slave address ........................................................................ 34 i 2 c clock stretching ...................................................................... 34 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 3 table of contents ( continued) i 2 c general call address .................................................................. 34 i 2 c communication speed ................................................................. 35 i 2 c communication protocols ............................................................... 35 writing to a single register ................................................................. 35 writing to sequential registers .............................................................. 36 writing multiple bytes using register-data pairs ....................................................................... 38 reading from a single register .............................................................. 38 reading from sequential registers ............................................................... 40 engaging hs mode for operation up to 3.4mhz ................................................. 41 i 2 c watchdog timer (wdtmr) ................................................................ 41 component selection ........................................................................ 41 input capacitance ........................................................................ 41 output capacitance ....................................................................... 41 inductors ............................................................................... 42 selection guide .............................................................................. 42 registers ................................................................................... 42 register map ............................................................................... 42 register details ............................................................................. 43 vout register ........................................................................... 43 vout_dvs register ...................................................................... 43 control1 register ...................................................................... 44 control2 register ...................................................................... 45 chipid1 register ......................................................................... 45 chipid2 register ......................................................................... 46 pcb layout guideline ......................................................................... 46 typical operating circuit ....................................................................... 47 ordering information .......................................................................... 48 package information .......................................................................... 48 chip information .............................................................................. 48 revision history .............................................................................. 49 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 4 list of figures list of tables figure 1. max8973_ functional block diagram ..................................................... 27 figure 2. typical applications circuit .............................................................. 28 figure 3. soft-start discharge ................................................................... 30 figure 4. rotational phase spreading algorithm ..................................................... 31 figure 5. i 2 c example system .................................................................. 33 figure 6. start and stop conditions ........................................................... 33 figure 7. i 2 c acknowledge (a) and not-acknowledge (na) ............................................ 34 figure 8. slave address byte example ............................................................ 34 figure 9. writing to a single register with the write byte protocol ...................................... 36 figure 10. writing to sequential registers x to n .................................................... 37 figure 11. writing to multiple registers with the multiple byte register data pair protocol .................... 39 figure 12. reading from a single register with the read byte protocol .................................. 39 figure 13. reading continuously from sequential registers x to n ...................................... 40 figure 14. engaging hs mode .................................................................... 41 figure 15. max8973_ evkit layout recommendation ............................................... 47 table 1. MAX8973A enable truth table ........................................................... 29 table 2. biasen and startup delay truth table ..................................................... 29 table 3. MAX8973A startup and dvs ramp rates .................................................. 29 table 4. MAX8973A output discharge selection truth table ........................................... 29 table 5. MAX8973A soft-stop slew rate .......................................................... 30 table 6. default output voltage settings ........................................................... 30 table 7. dvs response to decrease in target v out ........................................... 31 table 8. MAX8973A inductor parameters .......................................................... 31 table 9. enhanced transient response settings .................................................... 32 table 10. max8973_ i 2 c slave addresses ......................................................... 34 table 11. max8973_ selection guide ............................................................. 42 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 5 electrical characteristics (v in_ = v cc = v en = 3.6v, v agnd = v pg_ = v biasen = v dvs = 0v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . in_, v cc , v dd to pg_ ........................................... -0.3v to +6v sda, scl to agnd .................................. -0.3v to (v dd + 0.3v) lx_ to pg_ ............................................... -0.3v to (v in_ + 0.3v) dvs, en, biasen to agnd .................... -0.3v to (v cc + 0.3v) sns+, out to agnd ............................... -0.3v to (v cc + 0.3v) pg_, sns- to agnd ............................................ -0.3v to +0.3v in_ to v cc ...................................................... ...... -0.3v to +0.3v rms lx_ current (per bump) .............................................. 1.6a continuous power dissipation (t a = +70c) 28-bump wlp 0.4mm pitch (derate 20.4mw/c above +70c) ................................ 1.63w operating temperature range ........................... -40c to +85c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +150c bump temperature (soldering, reflow) ............................ +260c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) junction-to-ambient thermal resistance ( ja ) (note 1) ........................................... 49c/w junction-to-case thermal resistance ( jc ) (note 1) .......................................... 10c/w absolute maximum ratings parameter conditions min typ max units input supplies v cc and in_ operating range 2.6 4.5 v v cc and in_ undervoltage lockout (uvlo) threshold v in_ falling 2.45 2.5 2.55 v v cc and in_ uvlo hysteresis 200 mv v cc and in_ shutdown supply current en = 0 t a = +25oc 2 3 a t a = +85oc 2.5 v cc and in_ bias enable supply current en = 0, biasen = 1, no switching 34 50 a v cc and in_ operating supply current fpwm_en = 0, v out = 1.2v, no load, no switching, ckadv=11 (etr disabled) 135 190 a fpwm_en = 0, v out = 1.2v, no load, no switching, ckadv = 00 (etr enabled) 225 345 a fpwm_en = 1, v out = 1.2v, no load, f sw = 2mhz/phase, inductor losses included 25 ma logic interface (dvs, en, biasen) logic input high voltage (v ih ) 1.4 v logic input low voltage (v il ) 0.4 v input leakage current enpd_en = 1 -1 0.001 +1 a en logic input pulldown resistor controlled by serial interface command: enpd_en = 0 250 500 750 k? MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 6 electrical characteristics (continued) (v in_ = v cc = v en = 3.6v, v agnd = v pg_ = v biasen = v dvs = 0v, v en = 3.6v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter conditions min typ max units i 2 c serial interface sda and scl i/o stages scl, sda input high voltage (v ih ) v dd = 1.8v 0.7 x v dd v scl, sda input high voltage (v il ) v dd = 1.8v 0.3 x v dd v scl, sda input hysteresis (v hys ) 0.2 x v dd v scl, sda input current (i i ) -10 +10 a sda output low voltage (v ol ) sinking 20ma 0.4 v scl, sda pin capacitance (c i ) 10 pf output fall time from v ih to v il (t of ) 120 ns scl watchdog timer period wdtmr = 0 = off (default setting) ms wdtmr = 1 24.5 35 45.5 i 2 c-compatible interface timing for standard, fast mode, and fast mode plus clock frequency (f scl ) (note 3) 1000 khz hold time (repeated) start condition (t hd;sta ) (note 3) 0.26 s clk low period (t low ) (note 3) 0.5 s clk high period (t high ) (note 3) 0.26 s set-up time repeated start condition (t su;sta ) (note 3) 0.26 s data hold time (t hd;dat ) (note 3) 0 s data setup time (t su;dat ) (note 3) 50 ns setup time for stop condition (t su;sto ) (note 3) 0.26 s bus free time between stop and start (t buf ) (note 3) 0.5 s capacitive load for each bus line (c b ) (note 3) 550 pf maximum pulse width of spikes that must be suppressed by the input filter (note 3) response time of comparators 50 ns i 2 c-compatible interface timing for high-speed mode c b = 100pf clock frequency (f scl ) 3.4 mhz setup time repeated start condition (t su;sta ) 160 ns hold time repeated start condition (t hd;sta ) 160 ns MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 7 electrical characteristics (continued) (v in_ = v cc = v en = 3.6v, v agnd = v pg_ = v biasen = v dvs = 0v, v en = 3.6v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter conditions min typ max units clock low period (t low ) 160 ns clock high period (t high ) 60 ns data setup time (t su;dat ) 10 ns data hold time (t hd;dat ) 0 70 ns minimum scl rise time (t rcl,min ) 10 ns maximum scl rise time (t rcl,max ) 40 ns minimum rise time of scl signal after a repeated start condition and after an acknowledge bit (t rcl1,min ) 10 ns maximum rise time of scl signal after a repeated start condition and after an acknowledge bit (t rcl1,max ) 80 ns minimum scl fall time (t fcl,min ) 10 ns maximum scl fall time (t fcl,max ) 40 ns minimum sda rise time (t rda,min ) 10 ns maximum sda rise time (t rda,max ) 80 ns minimum sda fall time (t fda,min ) 10 ns maximum sda fall time (t fda,max ) 80 ns setup time for stop condition (t su;sto ) 160 ns capacitive load for each bus line (c b ) (note 3) 100 pf maximum pulse width of spikes that must be suppressed by the input filter 10 ns c b = 400pf clock frequency (f scl ) (note 3) 1.7 mhz setup time repeated start condition (t su;sta ) (note 3) 160 ns hold time repeated start condition (t hd;sta ) (note 3) 160 ns clock low period (t low ) (note 3) 320 ns MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 8 electrical characteristics (continued) (v in_ = v cc = v en = 3.6v, v agnd = v pg_ = v biasen = v dvs = 0v, v en = 3.6v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter conditions min typ max units clock high period (t high ) (note 3) 120 ns data setup time (t su;dat ) (note 3) 10 ns data hold time (t hd;dat ) (note 3) 0 150 ns minimum scl rise time (t rcl,min ) 20 ns maximum scl rise time (t rcl,max ) 80 ns minimum rise time of scl signal after a repeated start condition and after an acknowledge bit (t rcl1,min ) 20 ns maximum rise time of scl signal after a repeated start condition and after an acknowledge bit (t rcl1,max ) 160 ns minimum scl fall time (t fcl,min ) 20 ns maximum scl fall time (t fcl,max ) 80 ns minimum sda rise time (t rda,min ) 20 ns maximum sda rise time (t rda,max ) 160 ns minimum sda fall time (t fda,min ) 20 ns maximum sda fall time (t fda,max ) 160 ns setup time for stop condition (t su;sto ) (note 3) 160 ns capacitive load for each bus line (c b ) (note 3) 400 pf maximum pulse width of spikes that must be suppressed by the input filter (note 3) 10 ns step-down converter minimum output capacitance required for stability (note 3) actual output capacitance, sum of all 3 phases v out = 0.60625v to 1.4v i out = 0 to 9a 24.5 f out voltage range 6.25mv steps, 7 bits, monotonic 0.60625 1.4 v MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 9 electrical characteristics (continued) (v in_ = v cc = v en = 3.6v, v agnd = v pg_ = v biasen = v dvs = 0v, v en = 3.6v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter conditions min typ max units out voltage accuracy no load, v cc = v in_ = 2.6v to 4.5v, v out = 1.2v, fpwm_en = 1 t a = +25oc -0.5 +0.5 % no load, v cc = v in_ = 2.6v to 4.5v, v out = 1.2v, fpwm_en = 1 t a = -40oc to +85oc -0.8 +0.8 no load, v cc = v in_ = 2.6v to 4.5v, v out = 0.60625v, fpwm_en = 1 t a = -40oc to +85oc -1.5 +1.5 no load, v cc = v in_ = 2.6v to 4.5v, v out = 1.4v, fpwm_en = 1 t a = -40oc to +85oc -1.25 +1.25 load regulation -0.001 v/a output voltage slew rate ramp[1:0] = 11 200 mv/s ramp[1:0] = 10 50 ramp[1:0] = 01 25 ramp[1:0] = 00 12.5 peak current limit each phase MAX8973A 3.72 4 4.28 a nmos current limit each phase, valley current after pmos current limit and v out < 75% of target 55% of i lim setting a negative current limit fpwm_en = 1 or ramping down output voltage, each phase -1.33 a n-channel mosfet zero-crossing threshold 50 ma switching frequency per phase fpwm_en = 1 1.9 2 2.1 mhz soft-start delay biasen = 0, from en rising to v out at 10% 240 s biasen = 1, from en rising to v out at 10% 20 s MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 10 note 2: 100% production tested at t a = +25c, limits over the operating range are guaranteed by design. note 3: guaranteed by design, not production tested. electrical characteristics (continued) (v in_ = v cc = v en = 3.6v, v agnd = v pg_ = v biasen = v dvs = 0v, v en = 3.6v, t a = -40c to +85c, unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter conditions min typ max units soft-start ramp time from v out = 10% to 90%, ramp[1:0] = 0b11 200mv/s slew rate, v out set to 1v 4 s from v out = 10% to 90%, ramp[1:0] = 0b10, 0b01, or 0b00 20mv/s slew rate, v out set to 1v 40 lx p-channel mosfet on-resistance each phase, in_ to lx_, i lx_ = -200ma 50 90 m? lx n-channel mosfet on-resistance each phase, fpwm_en = 0, lx_ to pgnd, i lx_ = 200ma 25 45 m? lx leakage v lx_ = 5.5v or 0v t a = +25oc -1 +0.03 +1 a t a = +85oc 0.25 out discharge resistance during shutdown from out to agnd 100 ? sns+ input impedance 340 k? sns- input impedance 280 k? remote sense compensation range from out to sns+ 100 mv from gnd to sns- -100 mv out input impedance 53 k? thermal protection thermal shutdown threshold 160 oc thermal shutdown threshold hysteresis 20 oc MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 11 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) shutdown supply current vs. input voltage max8973 toc01 input voltage (v) supply current (a) 5.0 4.5 0.5 1.0 1.5 2.5 3.0 3.5 2.0 4.0 1 2 3 4 5 6 7 8 0 0 5.5 en = biasen = 0 t a = +25c t a = -40c t a = +85c standby supply current vs. input voltage max8973 toc02 input voltage (v) supply current (a) 5.0 4.5 0.5 1.0 1.5 2.5 3.0 3.5 2.0 4.0 5 10 15 20 25 30 40 35 45 50 0 0 5.5 en = agnd, biasen = v cc t a = +25c t a = +85c t a = -40c operating supply current vs. input voltage max8973 toc03 input voltage (v) supply current (a) 5.0 4.5 4.0 3.5 3.0 25 50 75 100 125 150 175 200 225 250 0 2.5 5.5 en = v cc , fpwm_en = 0, snsen = 0 t a = -40c t a = +25c t a = +85c operating supply current vs. input voltage max8973 toc04 input voltage (v) supply current (a) 5.0 4.5 4.0 3.5 3.0 25 50 75 100 125 150 175 200 225 250 0 2.5 5.5 en = 1, fpwm_en = 0, snsen = 1 t a = -40c t a = +25c t a = +85c operating supply current vs. input voltage max8973 toc05 input voltage (v) supply current (a) 5.0 4.5 4.0 3.5 3.0 20 22 24 26 28 30 32 34 36 38 18 2.5 5.5 en = 1, fpwm_en = 1, snsen = 0, no load includes inductor core loss t a = -40c t a = +25c t a = +85c efficiency vs. output current (v out = 1.4v) max8973 toc06 output current (a) efficiency (%) 10.10.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 en = 1, snsen = 0 fpwm_en = 1 fpwm_en = 0 v in = 3.0v v in = 3.6v v in = 4.2v efficiency vs. output current (v out = 1.2v) max8973 toc07 output current (a) efficiency (%) 10.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 fpwm_en = 1 fpwm_en = 0 v in = 3.0v v in = 3.6v v in = 4.2v en = 1, snsen = 0 efficiency vs. output current (v out = 1.1v) max8973 toc08 output current (a) efficiency (%) 10.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 fpwm_en = 1 fpwm_en = 0 v in = 3.0v v in = 3.6v v in = 4.2v en = 1, snsen = 0 efficiency vs. output current (v out = 1.0v) max8973 toc09 output current (a) efficiency (%) 10.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 fpwm_en = 1 v in = 3.0v v in = 3.6v v in = 4.2v en = 1, snsen = 0 fpwm_en = 0 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 12 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) efficiency vs. output current (v out = 0.9v) max8973 toc10 output current (a) efficiency (%) 10.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 fpwm_en = 1 v in = 3.0v v in = 3.6v v in = 4.2v en = 1, snsen = 0 fpwm_en = 0 efficiency vs. output current (v out = 0.8v) max8973 toc11 output current (a) efficiency (%) 10.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 fpwm_en = 1 v in = 3.0v v in = 3.6v v in = 4.2v en = 1, snsen = 0 fpwm_en = 0 efficiency vs. output current (v out = 0.6v) max8973 toc12 output current (a) efficiency (%) 10.1 0.01 0.001 10 20 30 40 50 60 70 80 90 100 0 0.0001 10 fpwm_en = 1 v in = 3.0v v in = 3.6v v in = 4.2v en = 1, snsen = 0 fpwm_en = 0 output voltage vs. output current (v out = 1.4v) max8973 toc13 output current (a) output voltage (v) 10.1 0.01 0.001 1.392 1.394 1.396 1.398 1.400 1.402 1.404 1.406 1.408 1.410 1.390 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 0 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 1.2v) max8973 toc14 output current (a) output voltage (v) 10.1 0.01 0.001 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 1.208 1.210 1.190 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 0 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 1.1v) max8973 toc15 output current (a) output voltage (v) 10.1 0.01 0.001 1.092 1.094 1.096 1.098 1.100 1.102 1.104 1.106 1.108 1.110 1.090 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 0 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 1.0v) max8973 toc16 output current (a) output voltage (v) 10.1 0.01 0.001 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 0.988 0.990 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 0 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 0.9v) max8973 toc17 output current (a) output voltage (v) 10.1 0.01 0.001 0.890 0.892 0.894 0.896 0.898 0.900 0.902 0.904 0.906 0.908 0.888 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 0 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 0.8v) max8973 toc18 output current (a) output voltage (v) 10.1 0.01 0.001 0.790 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0.808 0.788 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 0 measured at point-of-load snsen = 0 snsen = 1 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 13 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) output voltage vs. output current (v out = 0.6v) max8973 toc19 output current (a) output voltage (v) 10.1 0.01 0.001 0.596 0.598 0.600 0.602 0.602 0.604 0.606 0.608 0.610 0.612 0.594 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 0 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 1.4v) max8973 toc20 output current (a) output voltage (v) 10.1 0.01 0.001 1.392 1.394 1.396 1.398 1.400 1.402 1.404 1.406 1.408 1.410 1.390 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 1 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 1.2v) max8973 toc21 output current (a) output voltage (v) 10.1 0.01 0.001 1.190 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 1.208 1.188 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 1 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 1.1v) max8973 toc22 output current (a) output voltage (v) 10.1 0.01 0.001 1.090 1.092 1.094 1.096 1.098 1.100 1.102 1.104 1.106 1.108 1.088 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 1 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 1.0v) max8973 toc23 output current (a) output voltage (v) 10.1 0.01 0.001 0.990 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 1.008 0.988 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 1 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 0.9v) max8973 toc24 output current (a) output voltage (v) 10.1 0.01 0.001 0.890 0.892 0.894 0.896 0.898 0.900 0.902 0.904 0.906 0.908 0.888 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 1 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 0.8v) max8973 toc25 output current (a) output voltage (v) 10.1 0.01 0.001 0.790 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0.808 0.788 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 1 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. output current (v out = 0.6v) max8973 toc26 output current (a) output voltage (v) 10.1 0.01 0.001 0.596 0.598 0.600 0.602 0.604 0.606 0.608 0.610 0.612 0.614 0.590 0.594 0.592 0.0001 10 v in = 4.2v v in = 3.6v v in = 3.0v en = 1, fpwm_en = 1 measured at point-of-load snsen = 0 snsen = 1 output voltage vs. input voltage (v out = 1.4v) max8973 toc27 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 1.390 1.392 1.394 1.396 1.398 1.400 1.402 1.404 1.406 1.408 1.388 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 0 i out = 1a i out = 1ma i out = 100ma i out = 9a MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 14 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) output voltage vs. input voltage (v out = 1.4v) max8973 toc28 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 1.390 1.392 1.394 1.396 1.398 1.400 1.402 1.404 1.406 1.408 1.388 2.5 5.5 en = 1, fpwm_en = 0, snsen = 1 measured at point of load i out = 1ma i out = 100ma i out = 1a i out = 9a output voltage vs. input voltage (v out = 1.2v) max8973 toc29 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 1.190 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 1.208 1.188 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 0 i out = 1a i out = 1ma i out = 100ma i out = 9a output voltage vs. input voltage (v out = 1.2v) max8973 toc30 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 1.190 1.192 1.194 1.196 1.198 1.200 1.202 1.204 1.206 1.208 1.188 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 0 i out = 1ma i out = 1a i out = 100ma i out = 9a output voltage vs. input voltage (v out = 1.1v) max8973 toc31 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 1.088 1.090 1.092 1.094 1.096 1.098 1.100 1.102 1.104 1.106 1.086 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 0 i out = 1a i out = 1ma i out = 100ma i out = 9a output voltage vs. input voltage (v out = 1.1v) max8973 toc32 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 1.088 1.090 1.092 1.094 1.096 1.098 1.100 1.102 1.104 1.106 1.086 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 1 i out = 1ma i out = 1a i out = 100ma i out = 9a output voltage vs. input voltage (v out = 1.0v) max8973 toc33 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 0.988 0.990 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 0.986 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 0 i out = 1a i out = 1ma i out = 100ma i out = 9a output voltage vs. input voltage (v out = 1.0v) max8973 toc34 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 0.988 0.990 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 0.986 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 1 i out = 1ma i out = 1a i out = 100ma i out = 9a output voltage vs. input voltage (v out = 0.9v) max8973 toc35 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 0.888 0.890 0.892 0.894 0.896 0.898 0.900 0.902 0.904 0.906 0.886 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 0 i out = 1a i out = 1ma i out = 100ma i out = 9a output voltage vs. input voltage (v out = 0.9v) max8973 toc36 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 0.888 0.890 0.892 0.894 0.896 0.898 0.900 0.902 0.904 0.906 0.886 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 1 i out = 1ma i out = 1a i out = 100ma i out = 9a MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 15 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) output voltage vs. input voltage (v out = 0.8v) max8973 toc37 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 0.788 0.790 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0.786 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 0 i out = 1a i out = 1ma i out = 100ma i out = 9a output voltage vs. input voltage (v out = 0.8v) max8973 toc38 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 0.788 0.790 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0.786 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 1 i out = 1ma i out = 1a i out = 100ma i out = 9a output voltage vs. input voltage (v out = 0.6v) max8973 toc39 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 0.610 0.612 0.592 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 0 i out = 1a i out = 1ma i out = 100ma i out = 9a output voltage vs. input voltage (v out = 0.6v) max8973 toc40 input voltage (v) output voltage (v) 5.0 4.5 4.0 3.5 3.0 0.594 0.596 0.598 0.600 0.602 0.604 0.606 0.608 0.610 0.612 0.592 2.5 5.5 measured at point of load en = 1, fpwm_en = 0, snsen = 1 i out = 1ma i out = 1a i out = 100ma i out = 9a code output voltage (v) 240 224 192 208 160 176 144 128 256 output voltage vs. code max8973 toc41 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.5 en =1, fpwm_en = 0 or 1, snsen = 0 or 1 switching frequency vs. input voltage max8973 toc42 input voltage (v) switching frequency (mhz) 5.0 4.5 4.0 3.5 3.0 1.78 1.80 1.83 1.85 1.88 1.90 1.93 1.95 1.98 2.00 2.03 2.05 1.75 2.5 5.5 en = 1, fpwm_en = 1 freqshift = 0 freqshift = 1 t a = -40c t a = +25c t a = +85c switching frequency vs. output voltage max8973 toc43 output voltage (v) switching frequency (mhz) 1.3 1.2 1.0 1.1 0.8 0.9 0.7 1.78 1.80 1.83 1.85 1.88 1.90 1.93 1.95 1.98 2.00 2.03 2.05 1.75 0.6 1.4 en = 1, fpwm_en = 1 freqshift = 0 freqshift = 1 t a = -40c t a = +25c t a = +85c switching frequency vs. output current (skip mode) max8973 toc44 output current (a) switching frequency (mhz) 1 0.10.01 0.001 0.001 0.01 0.1 1 10 0.0001 0.0001 10 en = 1, fpwm_en = 0, freqshift = 0 t a = -40c t a = +25c t a = +85c switching frequency vs. output current (pwm mode) max8973 toc45 output current (a) switching frequency (mhz) 10.1 0.001 0.01 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 1.80 0.0001 10 en = 1, fpwm_en = 1, freqshift = 0 t a = -40c t a = +25c t a = +85c MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 16 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) startup delay (biasen = 0) max8973 toc46 i in v out v en 2v/div 500mv/div 500ma/div 0v 0v 0a 40s/div fpwm_en = 0, i out = 0 startup delay (biasen = 1) max8973 toc47 i in v out v en 2v/div 500mv/div 500ma/div 0v 0v 0a 10s/div fpwm_en = 0, i out = 0 startup into 1ma load (biasen = 1) max8973 toc48 i in i out v out v en 2v/div 500mv/div 500ma/div 2ma/div 0v 0v 0a 0a 40s/div fpwm_en = 0, ramp[1:0] = 0b10 startup into 100ma load (biasen = 1) max8973 toc49 i in i out v out v en 2v/div 500ma/div 500mv/div 100ma/div 0v 0v 0a 0a 40s/div fpwm_en = 0, ramp[1:0] = 0b10 startup into 1a load (biasen = 1) max8973 toc50 i in i out v out v en 2v/div 500ma/div 500mv/div 500ma/div 0v 0v 0a 0a 40s/div fpwm_en = 0, ramp[1:0] = 0b10 startup into 9a load (biasen = 1) max8973 toc51 i in i out v out v en 2v/div 5a/div 500mv/div 5a/div 0v 0v 0a 0a 40s/div fpwm_en = 0, ramp[1:0] = 0b10 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 17 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) startup into a short circuit max8973 toc52 i in i out v out v en 2v/div 5a/div 500mv/div 5a/div 0v 0v 0a 0a 40s/div fpwm_en = 0, ramp[1:0] = 0b10, biasen = 1 soft-stop with 1ma load (soft-stop on, resistive discharge off) max8973 toc53 i lxc i lxb i lxa v out v en 2v/div 1a/div 1a/div 1v/div 0v 0v 0a 0a 1a/div 0a 20s/div soft-stop with 1ma load (soft-stop on, resistive discharge on) max8973 toc54 i lxc i lxb i lxa v out v en 2v/div 1a/div 1a/div 1v/div 0v 0v 0a 0a 1a/div 0a 20s/div soft-stop with 1ma load (soft-stop off, resistive discharge off) max8973 toc55 i lxc i lxb i lxa v out v en 2v/div 1a/div 1a/div 1v/div 0v 0v 0a 0a 1a/div 0a 20ms/div soft-stop with 1ma load (soft-stop off, resistive discharge on) max8973 toc56 i lxc i lxb i lxa v out v en 2v/div 1a/div 1a/div 1v/div 0v 0v 0a 0a 1a/div 0a 20ms/div skip mode output voltage ripple (i out = 10ma) max8973 toc57 i lxc i lxb i lxa v out ripple 500ma/div 500ma/div 500ma/div 10mv/div 1v 0a 0a 0a 100s/div fpwm_en = 0 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 18 typical operating characteristics (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) skip mode output voltage ripple (i out = 100ma) max8973 toc58 i lxc i lxb i lxa v out ripple 500ma/div 500ma/div 500ma/div 10mv/div 1v 0a 0a 0a 4s/div fpwm_en = 0 skip mode output voltage ripple (i out = 1a) max8973 toc59 i lxc i lxb i lxa v out ripple 500ma/div 500ma/div 500ma/div 10mv/div 1v 0a 0a 0a 1s/div fpwm_en = 0 output voltage ripple (i out = 9a) max8973 toc60 i lxc i lxb i lxa v out ripple 2a/div 2a/div 2a/div 10mv/div 1v 0a 0a 0a 1s/div fpwm_en = 0 or 1 pwm mode output voltage ripple (i out = 10ma) max8973 toc61 i lxc i lxb i lxa v out ripple 10mv/div 500ma/div 1v 0a 500ma/div 0a 500ma/div 0a 1s/div fpwm_en = 1 pwm mode output voltage ripple (i out = 100ma) max8973 toc62 i lxc i lxb i lxa v out ripple 10mv/div 500ma/div 1v 0a 500ma/div 0a 500ma/div 0a 1s/div fpwm_en = 1 pwm mode output voltage ripple (i out = 1a) max8973 toc63 i lxc i lxb i lxa v out ripple 10mv/div 500ma/div 1v 0a 500ma/div 0a 500ma/div 0a 1s/div fpwm_en = 1 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 19 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) max8973 toc64 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 40s/div i out = 100ma dynamic voltage scaling (skip mode, 12.5mv/s, fsr_en = 0) 0.8v 0.8v 1.2v max8973 toc65 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 100s/div i out = 100ma dynamic voltage scaling (skip mode, 12.5mv/s, fsr_en = 1) 0.8v 0.8v 1.2v max8973 toc66 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 40s/div i out = 100ma dynamic voltage scaling (skip mode, 25mv/s, fsr_en = 0) 0.8v 0.8v 1.2v max8973 toc67 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 100s/div i out = 100ma dynamic voltage scaling (skip mode, 25mv/s, fsr_en = 1) 0.8v 0.8v 1.2v max8973 toc68 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 40s/div i out = 100ma dynamic voltage scaling (skip mode, 50mv/s, fsr_en = 0) 0.8v 0.8v 1.2v max8973 toc69 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 100s/div i out = 100ma dynamic voltage scaling (skip mode, 50mv/s, fsr_en = 1) 0.8v 0.8v 1.2v MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 20 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) max8973 toc70 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 2a/div 0a 2a/div 0a 2a/div 0a 40s/div i out = 100ma dynamic voltage scaling (skip mode, 200mv/s, fsr_en = 0) 0.8v 0.8v 1.2v max8973 toc71 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 2a/div 0a 2a/div 0a 2a/div 0a 100s/div i out = 100ma dynamic voltage scaling (skip mode, 200mv/s, fsr_en = 1) 0.8v 0.8v 1.2v max8973 toc72 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 40s/div i out = 100ma dynamic voltage scaling (pwm mode, 12.5mv/s, fsr_en = 0 or 1) 0.8v 0.8v 1.2v max8973 toc73 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 40s/div i out = 100ma dynamic voltage scaling (pwm mode, 25mv/s, fsr_en = 0 or 1) 0.8v 0.8v 1.2v max8973 toc74 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 1a/div 0a 1a/div 0a 1a/div 0a 40s/div i out = 100ma dynamic voltage scaling (pwm mode, 50mv/s, fsr_en = 0 or 1) 0.8v 0.8v 1.2v max8973 toc75 i lxc i lxb i lxa v dvs v out 0v 500mv/div 2v/div 2a/div 0a 2a/div 0a 2a/div 0a 40s/div i out = 100ma dynamic voltage scaling (pwm mode, 200mv/s, fsr_en = 0 or 1) 0.8v 0.8v 1.2v MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 21 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) max8973 toc76 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 1.2v 1a/div 0a 1a/div 0a 1a/div 0a 10s/div fpwm_en = 0 ckadv[1:0] = 0b11 skip mode load transient response (etr off) 10ma 10ma 2a max8973 toc77 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 1.2v 1a/div 0a 1a/div 0a 1a/div 0a 10s/div fpwm_en = 0 ckadv[1:0] = 0b00, 0b01, or 0b10 skip mode load transient response (etr on) 10ma 10ma 2a max8973 toc78 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 1a/div 1.2v 0a 1a/div 0a 1a/div 0a 10s/div fpwm_en = 1 ckadv[1:0] = 0b11, forced pwm mode load transient response (etr off) 10ma 10ma 2a max8973 toc79 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 1a/div 1.2v 0a 1a/div 0a 1a/div 0a 10s/div fpwm_en = 1 ckadv[1:0] = 0b00, 0b01, or 0b10 forced pwm mode load transient response (etr on) 10ma 10ma 2a max8973 toc80 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 2a/div 1.2v 0a 2a/div 0a 2a/div 0a 10s/div fpwm_en = 0 ckadv[1:0] = 0b11 skip mode load transient response (etr off) 10ma 10ma 5a max8973 toc81 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 2a/div 1.2v 0a 2a/div 0a 2a/div 0a 10s/div skip mode load transient response (etr on, 75mv/s) 10ma 10ma 5a fpwm_en = 0 ckadv[1:0] = 0b00 or 0b10 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 22 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) max8973 toc82 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 2a/div 1.2v 0a 2a/div 0a 2a/div 0a 10s/div fpwm_en = 0 ckadv[1:0] = 0b01 skip mode load transient response (etr on, 150mv/s) 10ma 10ma 5a max8973 toc83 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 2a/div 1.2v 0a 2a/div 0a 2a/div 0a 10s/div fpwm_en = 1 ckadv[1:0] = 0b11 forced pwm mode load transient response (etr off) 10ma 10ma 5a max8973 toc84 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 1.2v 2a/div 0a 2a/div 0a 2a/div 0a 10s/div fpwm_en = 1 ckadv[1:0] = 0b00 or 0b10 forced pwm mode load transient response (etr on, 75mv/s) 10ma 10ma 5a max8973 toc85 i lxc i lxb i lxa i out v out 50mv/div ac-coupled 1.2v 2a/div 0a 2a/div 0a 2a/div 0a 10s/div fpwm_en = 1 ckadv[1:0] = 0b01 forced pwm mode load transient response (etr on, 150mv/s) 10ma 10ma 5a max8973 toc86 i lxc i lxb i lxa i out v out 100mv/div ac-coupled 1.2v 5a/div 0a 5a/div 0a 5a/div 0a 10s/div fpwm_en = 0 ckadv[1:0] = 0b11 skip mode load transient response (etr off) 1a 1a 9a max8973 toc87 i lxc i lxb i lxa i out v out 100mv/div ac-coupled 1.2v 5a/div 0a 5a/div 0a 5a/div 0a 10s/div fpwm_en = 0 ckadv[1:0] = 0b00 or 0b10 skip mode load transient response (etr on, 75mv/s) 1a 1a 9a MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 23 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) max8973 toc88 i lxc i lxb i lxa i out v out 100mv/div ac-coupled 1.2v 5a/div 0a 5a/div 0a 5a/div 0a 10s/div fpwm_en = 0 ckadv[1:0] = 0b01 skip mode load transient response (etr on, 150mv/s) 1a 1a 9a max8973 toc89 i lxc i lxb i lxa i out v out 100mv/div ac-coupled 1.2v 5a/div 0a 5a/div 0a 5a/div 0a 10s/div fpwm_en = 1 ckadv[1:0] = 0b11 forced pwm mode load transient response (etr off) 1a 1a 9a max8973 toc90 i lxc i lxb i lxa i out v out 100mv/div ac-coupled 1.2v 5a/div 0a 5a/div 0a 5a/div 0a 10s/div fpwm_en = 1 ckadv[1:0] = 0b00 or 0b10 forced pwm mode load transient response (etr on, 75mv/s) 1a 1a 9a max8973 toc91 i lxc i lxb i lxa i out v out 100mv/div ac-coupled 1.2v 5a/div 0a 5a/div 0a 5a/div 0a 10s/div fpwm_en = 1 ckadv[1:0] = 0b01 forced pwm mode load transient response (etr on, 150mv/s) 1a 1a 9a max8973 toc92 i out i in v out 1v/div 0v 10a/div 0a 5a/div 0a 2ms/div short-circuit response MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 24 typical operating characteristics (continued) (v in = 3.6v, v dd = 1.8v, v out = 1.2v, circuit of figure 4.) max8973 toc93 v in v out 10mv/div ac-coupled 1.2v 4.2v i out = 10ma 100s/div skip mode line transient response 3v 3v max8973 toc94 v in v out 10mv/div ac-coupled 1.2v 4.2v i out = 1a 100s/div skip mode line transient response 3v 3v max8973 toc95 v in v out 10mv/div ac-coupled 1.2v 4.2v i out = 10ma 100s/div forced pwm mode line transient response 3v 3v max8973 toc96 v in v out 10mv/div ac-coupled 1.2v 4.2v i out = 1a 100s/div forced pwm mode line transient response 3v 3v MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 25 pin confguration pin description pin name description a1, b1, b2 pgb power ground for phase b. pins a1, b1, and b2. local to phase b power devices. bypass inab (pin a4) and the phase b output capacitor to pgb (pins a1/b1/b2). connect all pg_ pins with a power gnd plane underneath the device for heatsinking purposes. a2, a3 lxb inductor connection for phase b. lxb connects to the drains of the internal p-channel and n-channel fets. lxb is high impedance in shutdown. a4 inab power supply input to phase a and b. pin a4 is local to phase b power devices. inab powers the internal p-channel and n-channel fets. bypass inab (pin a4) to pgb (pins a1/b1/b2) with a 10f ceramic capacitor as close as possible to the device. connect all in_ pins to the same power source. a5 inab power supply input to phase a and b. pin a5 is local to phase a power devices. inab powers the internal p-channel and n-channel fets. bypass inab (pin a5) to pgac (pins b7/c7) with a 10f ceramic capacitor as close as possible to the device. connect all in_ pins to the same power source. a6, a7 lxa inductor connection for phase a. lxa connects to the drains of the internal p-channel and n-channel fets. lxa is high impedance in shutdown. b3 sda serial data input/output. sda is compatible with 1.2v logic. b4 out buck converter output node. in addition to setting the regulation point of the converter , out also discharges the output capacitor when the converter is shutdown. connect out to common v out (at the local output capacitors). b5 sns+ output voltage remote sense positive input. connect sns+ to the positive terminal of the bulk capacitance at the load. route sns- and sns+ as a differential pair through the pcb. the remote sense feature may be disabled through software. top view (bumps side down) 123456 7 b a c d wl p MAX8973A lxb pgb v dd v cc inab ou t agnd inc pgb pgb scl n.c. inab sns+ sns- inc lxa dvs biasen lxc lxa lxc lxb sda en n.c. pgac pgac + MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 26 pin description (continued) pin name description b6 dvs dvs logic input. when dvs is low the output voltage is programmed by register 0x00h (v out ). when dvs is driven high to v cc , the output voltage is programmed by register 0x01h (vout_dvs). b7, c7 pgac power ground for phase a and c. pin b7 and c7 are local to phase a and c power devices. bypass inc (pins d4/d5) and the phase c output capacitor to pgac (pins b7/c7). bypass inab (pin a5 only) and the phase a output capacitor to pgac (pins b7/c7). connect all pg_ pins with a power gnd plane underneath the device for heatsinking. c1 scl serial clock input c2 v dd logic power supply input for serial interface. connect v dd to a 1.8v supply. bypass v dd to agnd with a 0.1f ceramic capacitor. c3 en en logic input. en enables buck converter. drive high to v cc to enable the buck converter. en has a 500k? resistor to agnd that is connected by default but can be disconnected through the serial interface. the en input is ord with the en bit in the control1 register in the MAX8973A. c4 agnd analog ground c5 sns- output voltage remote sense negative input. connect sns- to the negative terminal of the bulk capacitance at the load. route sns- and sns+ as a differential pair through the pcb. the remote sense feature may be disabled through software. c6 biasen biasen logic input. biasen enables the MAX8973A bias to allow for faster start-up when the en pin is driven high. drive high to v cc to enable the fast startup mode. the biasen input is ord with the biasen bit in the control register. d1, d3 n.c. connect to agnd. d2 v cc analog power supply bypass node. bypass v cc to agnd with a 1f ceramic capacitor. v cc is internally connected to inc (pin d4) through a 20? internal resistor . v cc supplies the internal reference, bias circuitry, feedback circuitry, and serial interface. d4, d5 inc power supply input to phase c. pins d4 and d5 are local to phase c power devices. inc powers the internal p-channel and n-channel fets. inc also power v cc through an on- chip 20? flter resistor. bypass inc (pins d4/d5) to pgac (pins b7/c7) with a 10f ceramic capacitor as close as possible to the device. connect all in_ pins to the same power source. d6, d7 lxc inductor connection for phase c. lxc connects to the drains of the internal p-channel and n-channel fets. lxc is high impedance in shutdown. MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 27 detailed description the MAX8973A high-effciency, three-phase, dc-dc step-down switching regulator with differential remote sensing combines ultra-high effciency and very fast transient response with world-class accuracy over load, line, and temperature. three-phase operation with 2mhz switching frequency for each phase allows the use of miniature external components. differential remote sensing improves output accuracy by providing a kelvin- sense connection directly at the load. total output error is less than 0.8% over line, and temperature. the MAX8973A supports up to a 3.4mhz i 2 c 3.0- compatible serial interface. the output voltage is programmable through the serial interface from 0.60625v to 1.4v in 6.25mv steps. operating modes and output voltage slew rates of the MAX8973A are also programmable through the serial interface. other features include internal soft-start control circuitry to reduce inrush current, overcurrent protection, overtemperature protection, and startup into a prebiased output. a user-enabled slew rate control ramps up and down the output voltage in a controlled manner. an option to slew the output voltage at 200mv/s is provided, allowing the output voltage to respond to step change commands in as little as 10s. figure 1. max8973_ functional block diagram phase a drivers inab pgac lxa 2x v in 2.6v to 4.5v v out 0.60625v to 1.4v (upto 9a) clock generator and control circuitry osc phase b drivers inab pgb 3x lxb 2x v in phase c drivers inc pgac lxc 2x v in en[0] ramp[1:0] registers voltage control, v ref , bias, etc. clock and data input/ output feedback network scl v dd v cc sda inc dvs agnd biasen en sns+ sns- out MAX8973A MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 28 figure 2. typical applications circuit v dd inab, inc v cc pgac, pgb agnd 3x 10f 6.3v 1608 li+/ li-poly bat 1f 6.3v 1005 3x 22f 6.3v 2012 c pol 22f to 88f v out 0.60625v to 1.4v (9a max) cpu core system power management 0.68h 4a i sat 27m 3225 sda scl sda scl gpio1* off p 0.1f 6.3v 0603 470 1005 470 1005 lxa en on MAX8973A lxb lxc out sns+ sns- vdd vdd 1.8v 0.68h 4a i sat 27m 3225 0.68h 4a i sat 27m 3225 gpio2* bias off biasen bias on gpio3* vout dvs vout_dvs MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 29 enabling the regulator the MAX8973A output is enabled by driving the en input high or by setting the en bit to a 1 with an i 2 c command. the en input and the en bit are logically ord. disable the regulator by driving the en input low and setting the en bit to a 0. table 1 shows the logic truth table for the hardware en input and i 2 c register bit. the register contents may be written at any time to confgure the MAX8973A output. startup delay (biasen) to reduce the startup delay in applications where the cpu core must turn on quickly, the biasen logic input is logically ord with the biasen register bit to set the delay, defned as en rising to the start of the v out ramp. the startup delay is 240s (typ) when both the biasen input and the biasen bit are low. delay is reduced to 20s (typ) when the biasen input is high or the biasen bit is set to 1. selecting the shorter 20s delay increases quiescent current consumption by 34a if the en input is low and the en bit is set to 0 (step-down regulator is off). table 2 provides the truth table for the biasen input and register bit. startup ramp rate the MAX8973A features selectable startup ramp rates. the startup ramp rate is programmed to 20mv/s by default, with an optional rate of 200mv/s. the ramp[1:0] bits in the control1 register select the startup ramp rate, as shown in table 3 on page 26. the ramp[1:0] bits control the dvs ramp rate, in addition to the startup ramp rate. the default setting for the ramp[1:0] bits is 0b10, which selects the 20mv/s startup ramp rate and the 50mv/s dvs ramp rate. when the fastest startup ramp rate is selected, the actual output voltage may ramp at a rate slower than 200mv/s when a charging a large output capacitance due to peak inductor current limit. disabling the regulator (active discharge) disable the MAX8973A step-down regulator output by driving the en logic input low and setting the en bit to 0. table 1 shows the truth table for enabling and disabling the converter. the MAX8973A provides two different mechanisms for discharging the output capacitance. a resistive discharge path discharges the MAX8973A output capacitance when the converter is disabled. the resistive discharge path is selected with the ad_en bit in the control2 register. in addition to the resistive discharge path, a soft-stop function actively pulls energy from the output capacitance, and recycles this energy back into the input capacitance and battery. the soft-stop function is enabled by setting the fsr_en bit in the control1 register to a 0. the soft-stop function discharges the output capacitance at a slew rate selected by the ramp[1:0] bits in the control1 register. table 4 shows the truth table for the active discharge functions. table 1. MAX8973A enable truth table table 3. MAX8973A startup and dvs ramp rates table 4. MAX8973A output discharge selection truth table table 2. biasen and startup delay truth table en (input) en (bit) regulator status 0 0 off 0 1 on 1 0 on 1 1 on biasen (pin) biasen (bit) startup delay (s) i cc (a) 0 0 240 2 0 1 20 34 1 0 20 34 1 1 20 34 ramp[1:0] startup ramp rate (mv/s) dvs ramp rate (mv/s) 0b00 20 12.5 0b01 20 25 0b10 20 50 0b11 200 200 ad_en (bit) fsr_en (bit) output discharge method 0 0 soft-stop only 0 1 none (load current only) 1 0 soft-stop and resistive 1 1 resistive only MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 30 soft-stop (active energy recovery) the MAX8973A features a soft-stop mechanism to actively discharge the output capacitance when the regulator is disabled. setting the fsr_en bit in the control1 register to a 0 enables the soft-stop function when the converter is disabled. soft-stop ramps down the target output voltage at a rate selected by the ramp[1:0] bits in the control1 register. table 5 lists the selectable soft- stop slew rates. figure 3 illustrates the soft-stop behavior. note that when the fastest soft-stop ramp rate is selected, the actual output voltage may ramp down at a rate slower than 200mv/s when a discharging a large output capacitance due to negative inductor current limit. the soft-stop function takes advantage of the switching converter topology, by operating the converter as a boost regulator to discharge the output capacitance and transfer the energy stored in the output capacitance into the input capacitance. the soft-stop function keeps the MAX8973A enabled until the output voltage is discharged to 100mv (typ), at which time resistive discharge starts, completely discharging the output capacitance to gnd. a negative inductor current limit protects the internal switches from excessive power dissipation while the soft- stop function is active. when discharging a large output capacitance, the negative current limit may determine the discharge ramp rate, rather than the value set by the ramp[1:0] settings in table 5 . resistive discharge setting ad_en = 1 in the control2 register connects a 100 pulldown resistor from out to agnd when the MAX8973A regulator is disabled. if ad_en = 0 and soft- stop is not enabled, the MAX8973A output drifts to gnd at a rate determined by the load current. setting the output voltage the MAX8973A features two registers for setting the output voltage, v out and v out_dvs . this fexibility in how the output voltage is set. either the v out (or v out_dvs ) register can be written repeatedly with the dvs input tied to a fxed logic state, or both registers can be written with the dvs logic input toggling between the two registers. the output voltage ramps to the new target voltage according to the ramp[1:0] settings shown in table 3 , regardless of which method is used to change the output voltage. dvs the MAX8973A output voltage toggles between two different voltage settings by driving the dvs logic input high or low. the dvs logic input selects the default power- up voltage or dynamically changes the output voltage setting between target voltages programmed through the serial interface. default power-up voltage the MAX8973A default output voltage is selected by driving the dvs logic input high or low prior to enabling the step-down regulator. table 6 lists the default voltage settings for the MAX8973A. the MAX8973A power-up voltages may be changed by writing new target output voltages to the vout register (dvs = agnd) and/or the vout_dvs register (dvs = v dd ) prior to driving the en pin high or setting the en bit = 1 to enable the step-down regulator. figure 3. soft-start discharge table 5. MAX8973A soft-stop slew rate table 6. default output voltage settings ramp[1:0] soft-stop ramp rate (mv/s) 0b00 20 0b01 20 0b10 20 0b11 200 part number default v out dvs = agnd dvs = v dd MAX8973A 1.0v 1.2v 12 3 20mv/s or 200mv/s 1.0v 1. normal operation 2. soft-stop 3. resistive discharge 0.1v 25mv MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 31 slew rate control the MAX8973A provides four programmable ramp rates for output voltage transitions between target codes. the output voltage is always actively ramped when the new target voltage is greater than the current output voltage. table 3 lists the four settings for dvs ramp rates, set by the ramp[1:0] bits in the control1 register. if the new target voltage is less than the current output voltage, the ramp-down response is determined by the state of the fsr_en and fpwm_en bits. table 7 below summarizes the MAX8973A response to a command to decrease the target output voltage. control scheme the MAX8973A three-phase step-down regulator operates with a pulse-skipping scheme under light-to- medium loads, and transitions to a 2mhz fxed-frequency switching scheme under moderate-to-heavy loading. alternatively, the MAX8973A may operate with forced- pwm mode under all loads, if confgured by setting the fpwm_en bit in the control1 register to a 1. modes of operation (skip, mid, ccm) under light loads, the MAX8973A operates in skip mode with rotational phase spreading. under rotational phase spreading, all three phases continue to switch in an interleaved manner, regardless of load. as load current increases, the switching pulses become more frequent. as load current continues to increase, the on-times of all three phases begin to overlap, but each phase continues pulse skipping when considered on an individual basis to maximize effciency. as load current continues to increase, the inductor currents lift off, and a seamless transition into ccm operation occurs. the MAX8973A switches at a fxed 2mhz per phase switching frequency while operating in ccm mode. once in ccm operation, as load current decreases and the inductor current in any phase triggers a zero-crossing, the step-down regulator seamlessly transitions back into pulse-skipping mode. in skip and mid modes, the amplitude of the inductor current pulses is fxed. in ccm mode, the switching frequency is fxed, and the peak-to-peak inductor ripple current depends on the duty cycle and inductance. modes of operation (fpwm) the MAX8973A step-down regulator operates in forced pwm mode, regardless of load current, by setting the fpwm_en bit in the control1 register to a 1. in forced pwm mode, the MAX8973A switches at a fxed 2mhz per phase under all load conditions. negative inductor current is allowed under light load conditions in forced pwm mode. current sensing the MAX8973A uses a lossless current-sensing scheme for control loop stability. the time constant of the inductance and the inductors dcr is matched to an internal rc network. the MAX8973A are factory trimmed for optimization with particular inductances and ranges of dcr. see table 8 on page 30 for a list of optimal inductor parameters for each version of the MAX8973A. the inductor[1:0] bits in the control2 register infuence the gain and slope compensation of the current sense signal generated by the internal rc network used for sensing the inductor current. note: the inductor[1:0] settings should not be modifed while the converter is operating. table 7. dvs response to decrease in target v out figure 4. rotational phase spreading algorithm table 8. MAX8973A inductor parameters fsr_en fpwm_en dvs response 0 0 output ramps down at rate set by ramp[1:0] 0 1 output ramps down at rate set by ramp[1:0] 1 0 output decays at rate set by load current and output capacitance 1 1 output ramps down at rate set by ramp[1:0] part number l (h) dcr (m?) MAX8973A 0.68 27 phase a phase b phase c MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 32 maximum output current the MAX8973A maximum output current is infuenced by many parameters. use the following equation to determine the worst-case maximum output current: out outmax in out in v i n (plim (v v ) ) 2l v f = ?? where n = 3 (number of phases), plim = minimum peak current limit, v in = maximum input voltage, v out = maximum output voltage, l = minimum expected inductance, and f = minimum switching frequency. overload and short circuit protection the MAX8973A is protected against overloads with a peak current limit for each phase. in the event that an overload is applied to the output of the MAX8973A, the inductor current for each phase ramps up to the current limit to try to maintain the output in regulation. the MAX8973A is protected against a short-circuited output. in the event that the output is short-circuited, the inductor currents for each phase ramp up to the peak current limit, at which time the high-side mosfet is turned off. if v out < 75% of its target, the high-side is held off until the inductor current decreases to the nmos current limit, at which time the high-side is allowed to turn on again. this prevents inductor current from running away, and also reduces power dissipation by reducing the output power that the device can provide. the MAX8973A does not automatically turn off when the output is short- circuited. if the short-circuit is removed, the MAX8973A output ramps back up to the target voltage, and normal operation resumes. enhanced transient response (etr) the MAX8973A features an enhanced transient response circuit that is enabled through software. the enhanced transient response reduces the voltage droop during large load steps by temporarily allowing all three phases to fre in unison, slewing total inductor current faster than would normally be possible if all three phases continued to operate 120 out of phase. the enhanced transient response detector features two selectable sensitivity settings, which select the output voltage slew rate during load transients that triggers the etr circuit. the sensitivity of the etr detector is set by the ckadv[1:0] bits in the control2 register. table 9 summarizes the etr settings. remote sense the MAX8973A features differential remote sensing of the output voltage at the point of load. differential remote sensing compensates for voltage drops across the traces carrying high current from the MAX8973A output to the point of load. differential remote sensing is enabled by writing a 1 to the snsen bit in the control1 register. thermal protection the MAX8973A is protected against thermal overload with an internal temperature sensor. if the die temperature reaches 160c, the MAX8973A step-down regulator immediately turns off. the step-down regulator restarts when the die temperature decreases by 20c. i 2 c interface the MAX8973A step-down regulator provides an i 2 c 3.0-compatible (3.4mhz) serial interface. this 2-wire serial interface consists of a bidirectional serial data line (sda) and a serial clock line (scl). the MAX8973A acts as a slave-only device in normal mode where it relies on the master to generate a clock signal. the MAX8973A supports scl clock rates from 0hz to 3.4mhz. i 2 c is an open-drain bus and therefore sda and scl require pull- ups. optional resistors (24) in series with sda and scl protect the device inputs from high-voltage spikes on the bus lines. series resistors also minimize cross-talk and undershoot on bus signals. i 2 c interface features i 2 c revision 3.0-compatible serial communications channel 0hz to 100khz (standard mode) 0hz to 400khz (fast mode) 0hz to 1mhz (fast mode plus) 0hz to 3.4mhz (high-speed mode) does not utilize i 2 c clock stretching table 9. enhanced transient response settings ckadv[1:0] sensitivity v out 9w 00 high 75mv/s 01 low 150mv/s 10 high 75mv/s 11 off n/a MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 33 i 2 c system confguration the i 2 c bus is a multimaster bus. the maximum number of devices that can attach to the bus is only limited by bus capacitance. figure 5 shows an example of a typical i 2 c system. a device on the i 2 c bus that sends data to the bus in called a transmitter. a device that receives data from the bus is called a receiver. the device that initiates a data transfer and generates the scl clock signals to control the data transfer is a master. any device that is being addressed by the master is considered a slave. when the MAX8973A i 2 c-compatible interfaces are operating in normal mode, they are a slave on the i 2 c bus and it can be both a transmitter and a receiver. i 2 c interface power the MAX8973A i 2 c interface derives its power from an externally supplied power rail (v dd in figure 1 ). cycling v in_ resets the i 2 c registers. i 2 c data transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals. each transmit sequence is framed by a start (s) condition and a stop (p) condition. each data packet is nine bits long: eight bits of data followed by the acknowledge bit. data is transferred with the msb frst. i 2 c start and stop conditions when the serial interface is inactive, sda and scl idle high. a master device initiates communication by issuing a start condition. a start (s) condition is a high-to low transition on sda with scl high. a stop (p) condition is a low-to-high transition on sda, while scl is high ( figure 6 ). a start condition from the master signals the beginning of a transmission to the MAX8973A. the master terminates transmission by issuing a not-acknowledge followed by a stop condition. the stop condition frees the bus. to issue a series of commands to the slave, the master may issue repeated start (sr) commands instead of a stop command in order to maintain control of the bus. in general, a repeated start command is functionally equivalent to a regular start command. when a stop condition or incorrect address is detected, the MAX8973A internally disconnects scl from the serial interface until the next start condition, minimizing digital noise and feed-through. i 2 c acknowledge bit both the i 2 c bus master and the MAX8973A (slave) generate acknowledge bits when receiving data. the acknowledge bit is the last bit of each nine-bit data packet. to generate an acknowledge (a), the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse ( figure 7). to generate a not-acknowledge (na), the receiving device allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. figure 6. start and stop conditions figure 5. i 2 c example system master transmitte r/ receiver master transmitte r/ receiver slave transmitte r/ receiver slave receiver slave transmitter sda scl sp sr scl sda t hd;sta t hd;sta t su;sta t su;sto MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 34 monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. i 2 c slave address the MAX8973A implements 7-bit slave addressing. an i 2 c bus master initiates communication with a slave device (MAX8973A) by issuing a start condition followed by the slave address. as shown in table 10 , the MAX8973A responds to a single slave address. the MAX8973A does not acknowledge all addresses besides the ones listed in table 10 . figure 8 shows an example of the slave address byte format. as shown, the slave address byte consists of seven address bits and a read/write bit (r/ w ). after receiving the factory set slave address shown in table 10 , the MAX8973A issues an acknowledge by pulling sda low during the ninth clock cycle. i 2 c clock stretching the clock signal generation for the i 2 c bus is generally the responsibility of the master device. the i 2 c specifcation allows slow slave devices to alter the clock signal by holding down the clock line. the process in which a slave device holds down the clock line is called clock stretching. the MAX8973A does not support clock stretching. i 2 c general call address the MAX8973A does not implement the i 2 c specifcations general call address. if the MAX8973A sees the general call address (0b0000_0000), it issues a not acknowledge (na). figure 7. i 2 c acknowledge (a) and not-acknowledge (na) table 10. max8973_ i 2 c slave addresses figure 8. slave address byte example part number slave address write slave address read MAX8973A 0x36 0x37 not acknowledge (na) acknowledge (a) t hd,dat t su,dat 8 2 1 scl sda s 9 acknowledge r/w 0a 1 1 1 10 0 78 9 6 5 3 14 2 scl sda s MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 35 i 2 c communication speed the MAX8973A is compatible with all 4 communication speed ranges as defned by the revision 3.0 i 2 c specifcation: 0hz to 100khz (standard mode) 0hz to 400khz (fast mode) 0hz to 1mhz (fast mode plus) 0hz to 3.4mhz (high-speed mode) operating in standard mode, fast mode, and fast mode plus does not require any special protocols. the main consideration when changing the bus speed through this range is the combination of the bus capacitance and pullup resistors. higher time constants created by the bus capacitance and pullup resistance (c x r) slow the bus operation. therefore, when increasing bus speeds the pullup resistance must be decreased to maintain a reasonable time constant. see the pullup resistor sizing section of the i 2 c revision 3.0 specifcation for detailed guidance on the pullup resistor selection. in general, for bus capacitances of 200pf, a 100khz bus needs 5.6k pullup resistors, a 400khz bus needs about a 1.5k pullup resistors, and a 1mhz bus needs 680v pullup resistors. when the open-drain bus is low, the pullup resistor is dissipating power, and that lower value pullup resistors dissipate more power (v 2 /r). operating in high-speed mode requires some special considerations. for a full list of considerations see the i 2 c 3.0 specifcation. the major considerations with respect to the MAX8973A are: the i 2 c bus master use current source pullups to shorten the signal rise times. the i 2 c slave must use a different set of input flters on its sda and scl lines to accommodate for the higher bus speed. the communication protocols need to utilize the high- speed master code. at power-up and after each stop condition, the MAX8973A inputs flters are set for standard mode, fast mode, or fast mode plus (i.e. 0hz to 1mhz). to switch the input flters for high-speed mode, use the high-speed master code protocols that are described in the engaging hs mode for operation up to 3.4mhz section. i 2 c communication protocols the MAX8973A supports both writing and reading from its registers. the MAX8973A supports writing to a single register, writing multiple bytes using register-data pairs, reading from a single register, and reading from sequential registers. writing to a single register figure 9 shows the protocol for the i 2 c master device to write one byte of data to the MAX8973A. this protocol is the same as the smbus specifcations write byte protocol. the write byte protocol is as follows: 1) the master sends a start (s) command. 2) the master sends the 7-bit slave address followed by a write bit (r/w = 0). 3) the addressed slave asserts an acknowledge (a) by pulling sda low. 4) the master sends an 8-bit register pointer . 5) the slave acknowledges the register pointer . 6) the master sends a data byte. 7) the slave updates with the new data 8) the slave acknowledges or not acknowledges the data byte. the next rising edge on sda will load the data byte into its target register and the data will become active. 9) the master sends a stop (p) condition or a repeated start (sr) condition. issuing a p ensures that the bus input flters are set for 1mhz or slower operation. issuing an sr leaves the bus input flters in their current state. MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 36 figure 9. writing to a single register with the write byte protocol writing to sequential registers figure 10 shows the protocol for writing to a sequential registers. this protocol is similar to the write byte protocol, except the master continues to write after it sends the frst byte of data. when the master is done writing, it issues a stop (p) or repeated start (sr). this protocol is recommended when confguring the device during initialization. the writing to sequential registers protocol is as follows: 1) the master sends a start command (s). 2) the master sends the 7-bit slave address followed by a write bit (r/w=0). 3) the addressed slave asserts an acknowledge (a) by pulling sda low. 4) the master sends an 8-bit register pointer . 5) the slave acknowledges the register pointer . 6) the master sends a data byte. 7) the slave acknowledges the data byte. the next rising edge on sda will load the data byte into its target register and the data will become active. 8) steps 6 to 7 are repeated as many times as the master requires. 9) during the last acknowledge related clock pulse, the master may issue an acknowledge or a not-acknowledge. 10) the master sends a stop condition (p) or a repeated start condition (sr). issuing a p ensures that the bus input flters are set for 1mhz or slower operation. issuing a repeated start leaves the bus input flters in their current state. s 17 11 88 1 slave address sda scl register pointer da ta a 11 a or na p or sr* number of bits 0a b1 b0 acknowledge a 78 9 master to slav e legend slave to master the da ta is loaded into the ta rget register and becomes active during this rising edge. *p forces the bus filters to switch to their 1mhz mode. sr leaves the bus filters in their current st at e. r/w MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 37 figure 10. writing to sequential registers x to n s 17 11 88 1 slave address register pointer xd ata x a a ? detail: detail: ? 1 number of bits 0a master to slav e legend slave to master r/w 88 1 da ta x+1d ata x+2 a a 1 number of bits a p number of bits 88 1 da ta n-1d ata n a 11 sda scl b1 b0 b9 acknowledge a 78 91 the da ta is loaded in to the ta rget register and becomes active during this rising edge. sda scl b1 b0 acknowledge a 78 9 the da ta is loaded in to the ta rget register and becomes active during this rising edge. *p forces the bus filters to switch to their 1mhz mode. sr leaves the bus filters in their current s tat e. MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 38 writing multiple bytes using register-data pairs figure 11 shows the protocol for the i 2 c master device to write multiple bytes to the MAX8973A using register- data pairs. this protocol allows the i 2 c master device to address the slave only once and then send data to multiple registers in a random order. registers may be written continuously until the master issues a stop condition. the multiple byte register-data pair protocol is as follows: 1) the master sends a start (s) command. 2) the master sends the 7-bit slave address followed by a write bit (r/w = 0). 3) the addressed slave asserts an acknowledge (a) by pulling sda low. 4) the master sends an 8-bit register pointer . 5) the slave acknowledges the register pointer . 6) the master sends a data byte. 7) the slave acknowledges the data byte. the next rising edge on sda loads the data byte into its target register and the data becomes active. 8) steps 5 to 7 are repeated as many times as the master requires. 9) the master sends a stop (p) condition. during the rising edge of the stop related sda edge, the data byte that was previously written is loaded into the target register and becomes active. reading from a single register figure 12 shows the protocol for the i 2 c master device to read one byte of data to the MAX8973A. this protocol is the same as the smbus specifcations read byte protocol. the read byte protocol is as follows: 1) the master sends a start (s) command. 2) the master sends the 7-bit slave address followed by a write bit (r/w = 0). 3) the addressed slave asserts an acknowledge (a) by pulling sda low. 4) the master sends an 8-bit register pointer . 5) the slave acknowledges the register pointer . 6) the master sends a repeated start (sr) command. 7) the master sends the 7-bit slave address followed by a read bit (r/w = 1). 8) the addressed slave asserts an acknowledge by pulling sda low. 9) the addressed slave places 8-bits of data on the bus from the location specifed by the register pointer. 10) the master issues a not-acknowledge (na). 11) the master sends a stop condition (p) or a repeated start (sr) condition. issuing a p ensures that the bus input flters are set for 1mhz or slower operation. issuing an repeated start leaves the bus input flters in their current state. note that every time the MAX8973A receives a stop (p), its register pointer is set to 0x00. if reading register 0x00 after a stop (p) has been issued, steps 1 to 6 in the above algorithm can be skipped. MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 39 figure 11. writing to multiple registers with the multiple byte register data pair protocol figure 12. reading from a single register with the read byte protocol s 17 11 81 1 slave address register pointer x slave address a1 sr number of bits 0a master to slav e legend slave to master 7 da ta x 8 1 a 1 na 1 *p forces the bus filters to switch to their 1mhz mode. sr leaves the bus filters in their current s tat e. r/w r/w 1 p or sr* s 17 11 88 1 slave address register pointer xd ata x a a ? detail: detail: ? 1 number of bits 0a master to slav e legend slave to master r/w 88 1 register pointer nd ata n a a 1 number of bits a p number of bits 88 1 register pointer zd ata z a 11 sda scl b1 b0 b9 acknowledge a 78 91 the da ta is loaded in to the ta rget register and becomes active during this rising edge. sda scl b1 b0 acknowledge a 78 9 the da ta is loaded in to the ta rget register and becomes active during this rising edge. MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 40 figure 13. reading continuously from sequential registers x to n reading from sequential registers figure 13 shows the protocol for reading from sequential registers. this protocol is similar to the read byte protocol except the master issues an acknowledge to signal the slave that it wants more datawhen the master has all the data it requires it issues a not-acknowledge (na) and a stop (p) to end the transmission. the continuous read from sequential registers protocol is as follows: 1) the master sends a start (s) command. 2) the master sends the 7-bit slave address followed by a write bit (r/w = 0). 3) the addressed slave asserts an acknowledge (a) by pulling sda low. 4) the master sends an 8-bit register pointer . 5) the slave acknowledges the register pointer . 6) the master sends a repeated start (sr) command. 7) the master sends the 7-bit slave address followed by a read bit (r/ w = 1). when reading the rtc timekeeping registers, secondary buffers are loaded with the timekeeping register data during this operation. 8) the addressed slave asserts an acknowledge (a) by pulling sda low. 9) the addressed slave places 8-bits of data on the bus from the location specifed by the register pointer. 10) the master issues an acknowledge (a) signaling the slave that it wishes to receive more data. 11) steps 9 and 10 are repeated as many times as the master requires. following the last byte of data, the master must issue a not acknowledge (na) to signal that it wishes to stop receiving data. 12) the master sends a stop (p) condition or a repeated start (sr) condition. issuing a stop (p) ensures that the bus input flters are set for 1mhz or slower operation. issuing an sr leaves the bus input flters in their current state. note that every time the MAX8973A receives a stop (p), its register pointer is set to 0x00. if reading register 0x00 after a stop has been issued, steps 1 to 6 in the above algorithm can be skipped. s 17 11 81 slave address register pointer x1 0a master to slav e legend slave to master r/w 7 slave address r/w 8 1 da ta x a a 1 number of bits 1 a 1 sr 88 1 da ta x+2d ata x+3 a a 1 number of bits 81 da ta x+2a 88 1 da ta n-1 da ta n a na 11 number of bits 81 da ta n-2a p or sr* *p forces the bus filters to switch to their 1mhz mode. sr leaves the bus filters in their current st at e. MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 41 engaging hs mode for operation up to 3.4mhz figure 14 shows the protocol for engaging hs-mode operation. hs-mode operation allows for a bus operating speed up to 3.4mhz. the engaging hs-mode protocol is as follows: 1) begin the protocol while operating at a bus speed of 1mhz or lower 2) the master sends a start command (s). 3) the master sends the 8-bit master code of 0b0000 1xxx where 0bxxx are dont care bits. 4) the addressed slave issues a not acknowledge (na). 5) the master may now increase its bus speed up to 3.4mhz and issue any read/write operation. the master may continue to issue high-speed read/write operations until a stop (p) is issued. issuing a stop (p) ensures that the bus input flters are set for 1mhz or slower operation. i 2 c watchdog timer (wdtmr) the MAX8973A features a 35ms watchdog timer that resets the i 2 c state machine in the event that the i 2 c bus gets hung. the i 2 c watchdog timer is enabled by writing a 1 to the wdtmr bit in the control2 register. when the i 2 c watchdog timer is enabled, an i 2 c start command begins the timer, a falling edge of scl clears the i 2 c watchdog timer, and an i 2 c stop command resets and disables the timer. component selection input capacitance the MAX8973A requires a 10f input bypass capacitor for each phase. each input capacitor must be placed as close as possible to the device. each input capacitor case size should be 0603 (eia)/1608 (metric) or larger to provide adequate effective capacitance and to allow lx traces to be routed under the input capacitors. phase a is bypassed from inab (bump a5) to pgac (bumps b7 and c7). phase b is bypassed from inab (bump a4) to pgb (bumps a1, b1, and b2). phase c is bypassed from inc (bumps d4 and d5) to pgac (bumps b7 and c7). output capacitance the MAX8973A requires local output capacitance in order to stabilize the converter and to limit the amplitude of output droop and soar during load transients and load release. use the following equation to calculate the absolute minimum output capacitance per phase required to limit the voltage droop during load transient events: 2 step out droop in out (l (i )) c (2 v (v v )) ? where c out = effective output capacitance per phase, l = inductance per phase, i step = transient load step per phase, v droop = voltage droop during load step, v in = input voltage, and v out = output voltage. this formula calculates the minimum theoretical capacitance required for an infnitely fast converter. for most designs, an effective capacitance per phase 50% greater than the calculated value should suffce. use the following equation to calculate output voltage soar during load release: 2 step soar out out (l (i )) v (2 c v ) = an 0805 (eia)/2012 (metric) 22f x5r capacitor for each phase is recommended at a minimum, regardless of load step amplitude. additional output capacitance may be placed at the point of load to further improve transient response. if remote capacitance is installed, ensure that the total local output capacitance is at least 2x the total remote capacitance to ensure that the MAX8973As control loop is not adversely affected by the remote capacitance. figure 14. engaging hs mode s 18 11 8 hs master code any read/write protocol followed by sr any read/write protocol followed by sr sr sr na sr master to slav e legend slave to master any read/write protocol p fast mode fast mode hs mode MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 42 inductors the MAX8973A control loop is infuenced by the inductance and dcr of the inductor. each MAX8973A version is factory-tuned for a particular inductance and dcr, where the dcr is considered to be the inductors dcr plus the trace resistance from inductor to the output capacitor for each phase. it is highly recommended that the inductance and dcr does not deviate from the recommendations in the data sheet. table 8 lists the inductor parameters for each MAX8973A version. refer to the max8973ev kit for a list of recommended inductors. the MAX8973A does not actively match inductor currents. inductor current matching between phases is largely determined by how well the dcr of the inductors match each other. saturation current and temperature rise current ratings for the inductor should also be considered. ensure that the inductors saturation current rating meets or exceeds the maximum value for the peak current limit in the electrical characteristics table. ensure that the temperature rise current rating for the inductor exceeds the maximum expect rms output current from the MAX8973A. table 11. max8973_ selection guide selection guide registers register map part number parameter i out_max default v out default v out_dvs l ideal dcr soft- start/stop ramp rate dvs slew rate i 2 c slave address MAX8973A 9a 1.0v 1.2v 0.68h 27m? 20mv/s 50mv/s 0x36/0x37 register address register name default contents bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) 0x00h vout 0x3fh en vout[6:0] 0x01h vout_ dvs 0xdfh rsvd vout_dvs[6:0] 0x02h control1 0x02h snsen fpwm_ en fsr_en ad_en biasen freq shift ramp [1:0] 0x03h control2 0x1dh rsvd wdtmr enpd_en rsvd ckadv [1:0] inductor [1:0] 0x04h chipid1 0x80h dietype[7:0] 0x05h chipid2 0x14h dash[3:0] mask rev[3:0] MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 43 register details vout register vout_dvs register register name vout address 0x00h reset value MAX8973A: 0x3fh type read/write special features reset upon v cc uvlo or thermal shutdown bit name description default 7 en converter enable (logically ord with en pin) 0 = converter is off 1 = converter is on 0b0 6:0 vout [6:0] output voltage selection 0x00 = 0.60625v 0x01 = 0.61250v 0x0f = 0.70000v 0x1f = 0.80000v 0x3f = 1.00000v 0x47 = 1.05000v 0x5f = 1.20000v 0x7f = 1.40000v 0b011 1111 (1.0v) (MAX8973A) register name vout_dvs address 0x01h reset value MAX8973A: 0xdfh type read/write special features reset upon v cc uvlo or thermal shutdown bit name description default 7 rsvd reserved 0b1 6:0 vout_dvs [6:0] output voltage selection 0x00 = 0.60625v 0x01 = 0.61250v 0x0f = 0.70000v 0x1f = 0.80000v 0x3f = 1.00000v 0x47 = 1.05000v 0x5f = 1.20000v 0x7f = 1.40000v 0b101 1111 (1.2v) (MAX8973A) MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 44 control1 register register name control1 address 0x02h reset value MAX8973A: 0x02h type read/write special features reset upon v cc uvlo or thermal shutdown bit name description default 7 sns_en remote sense enable 0 = remote sense circuit disabled. 1 = remote sense circuit enabled. 0b0 6 fpwm_en forced pwm mode enable 0 = automatic transition from skip mode to pwm mode with change in load current. 1 = forced pwm mode under all load conditions. 0b0 5 fsr_en active-low falling slew rate enable 0 = the slew rate control circuit is active when the output voltage is decreased. the desired regulation voltage is decreased at a rate set by ramp[1:0] and forced pwm mode is enabled so that negative inductor current can be used to pull energy out of the output capacitor. 1 = the slew rate control circuit is disabled when the output voltage is decreased. the desired regulation voltage is decreased at a rate set by ramp[1:0], but it is up to the external load to drain energy from the output capacitor in order to pull down on the output voltage. 0b0 4 ad_en output active discharge enable 0 = 100? discharge resistance is disabled when en is low. 1 = 100? discharge resistance is enabled when en is low. 0b0 3 biasen enables step-down regulator bias to reduce the time delay to begin the output voltage ramp. the biasen bit is logically ord with the biasen pin. 0 = ref, bias, etc. off when buck is disabled. startup delay is 240s (typ). 1 = ref, bias, etc. on when buck is disabled. startup delay is 20s (typ). 0b0 2 freqshift frequency shift 0 = 2mhz (typ) switching frequency per phase in ccm and fpwm modes. 1 = 1.82mhz (typ) switching frequency per phase in ccm and fpwm modes. 0b0 1:0 ramp[1:0] slew rate selection 00 = sets startup/softstop slew rate = 20mv/s and dvs slew rate = 12.5mv/s 01 = sets startup/softstop slew rate = 20mv/s and dvs slew rate = 25mv/s 10 = sets startup/softstop slew rate = 20mv/s and dvs slew rate = 50mv/s 11 = sets startup/softstop slew rate = 200mv/s and dvs slew rate = 200mv/s 0b10 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 45 control2 register chipid1 register register name control2 address 0x03h reset value MAX8973A: 0x1dh type read/write special features reset upon v cc uvlo or thermal shutdown bit name description default 7 rsvd reserved 0b0 6 wdtmr i 2 c watchdog timer enable 0 = scl watchdog timer is disabled. 1 = scl watchdog timer is enabled with a 35ms period. an i 2 c start (s) condition starts the timer. a falling edge of scl clears the watchdog timer. an i 2 c stop (p) condition stops and resets the timer. 0b0 5 enpd_en active-low enable for en pulldown resistance 0 = 500k? pulldown resistance from en to agnd is enabled. 1 = 500k? pulldown resistance from en to agnd is disabled. 0b0 4 rsvd reserved 0b1 3:2 ckadv[1:0] enhanced transient response enable and sensitivity selection 00 = enhanced transient response circuit is enabled and set for high sensitivity . 75mv/s output slew rate triggers the etr response. 01 = enhanced transient response circuit is enabled and set for low sensitivity . 150mv/s output slew rate triggers the etr response. 10 = enhanced transient response circuit is enabled and set for high sensitivity . 75mv/s output slew rate triggers the etr response. 11 = enhanced transient response circuit is disabled. 0b11 1:0 inductor [1:0] slope compensation adjustment and rcs gain for inductor dcr sensing 00 = slope compensation and rcs = nominal -30% 01 = nominal 10 = slope compensation and rcs = nominal + 30% 11 = slope compensation and rcs = nominal + 60% 0b01 register name chipid1 address 0x04h reset value 0x80h type read only special features read only bit name description default 7:0 dietype [7:0] die type 0b1000 0000 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 46 chipid2 register pcb layout guideline the MAX8973A wlp package and bump confguration allows for a small total pcb area. the following recommendations for pcb layout are provided to minimize pcb area and to provide optimal performance from the MAX8973A. careful pcb layout is important for minimizing ground bounce and noise. figure 15 is an example layout showing the critical power components for the MAX8973A. the arrangement of components not shown in figure 15 is less critical. refer to the MAX8973A ev kit for a complete pcb layout example. use the following list of guidelines in addition to application note 1891: wafer-level packaging (wlp) and its applications ( www.maximintegrated.com/ucsp ) to layout the MAX8973A pcb. the following guidelines are arranged in terms of priority from most critical to least critical: 1) place cina as close to inab and pgac as possible. place cinb as close to inab and pgb as possible. place cinc as close to inc and pgac as possible. each phases input capacitor delivers a high di/dt current pulse when the high-side mosfet turns on. it is essential that parasitic inductance in the power input traces be minimized for high effciency and reliability. 2) minimize the trace length from each phases output capacitor gnd terminal to the input capacitors gnd terminal for that same phase. this minimizes the area of the current loop when the high-side mosfet is conducting. keep all sensitive signals, such as feedback nodes outside of these current loops with as much isolation as your design allows. 3) minimize the trace impedance from lx_ to each phases inductor and from each inductor to the output capacitor for each phase. this minimizes the area of each current loop and minimizes lx trace resistance and stray capacitance to achieve optimal effciency. keep all sensitive signals, such as feedback nodes outside of these current loops and away from the lx switching voltage with as much isolation as your design allows. 4) create a pgnd plane on the 2nd layer of the pcb immediately below the power components and bumps carrying high switching currents. this reduces parasitic inductance in the traces carrying high currents and shields signals on inner pcb layers from the switching waveforms on the top layer of the pcb. 5) conn ect the feedback terminal (out) to the local output capacitors for phase a and phase c. the out connection to the local output capacitors should be placed as close to the MAX8973A as possible to minimize the effects of voltage drop in the output trace connected to the load. register name chipid2 address 0x05h reset value 0x14h type read only special features read only bit name description default 7:4 dash[3:0] 0001 = MAX8973A 0b0001 3:0 rsvd reserved 0b0100 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 47 figure 15. max8973_ evkit layout recommendation typical operating circuit 6) place the v cc bypass capacitor as close to the MAX8973A as possible. noise coupling into v cc may disturb the reference and bias circuitry of the MAX8973A if this capacitor is installed away from the device. 7) create a small agnd island for the v cc and v dd bypass capacitors. connect this agnd island to the MAX8973A pgnd plane for phase a and phase c, between the pgnd terminals of the phase a and phase c output capacitors. this results in the most accurate sensing of the output voltage by the local feedback loop (out to agnd). 8) each of the MAX8973A bumps has approximately the same ability to remove heat from the die. connect as much metal as possible to each bump to minimize the ja associated with the MAX8973A. 9) conn ect the power output of each phase together on a power plane with as many vias as practical to minimize trace impedance. v dd v cc inab, inc pgac, pgb agnd 3x 10f 3x 22f 0.1f v out 0.60625v to 1.4v (9a max) cpu core 0.68h v in 2.6v to 4.5v v dd 1.8v sda scl 0.1f 1f lxa en biasen dvs n.c. MAX8973A 0.68h lxb 0.68h lxc out sns+ sns- MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
maxim integrated 48 chip information process: bicmos ordering information package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffx character, but the drawing pertains to the package regardless of rohs status. part default v out i out,max pin- package MAX8973Aewi+t 1.0v/1.2v 9a 28 wlp package type package code outline no. land pattern no. 28 wlp w282b3+1 21-0627 refer to application note 1891 e d aaaa pin 1 indicator marking a3 a2 a1 a see note 7 0.05 s s e e1 d1 sd b se 0.05 m s ab b a side view a top view bottom view a 1 d c b 1 765432 title document control no. rev. 1 1 approval common dimensions a a2 a1 a3 b e1 d1 e sd se 0.05 0.03 0.03 basic ref basic min max max min e d pkg. code depopulated bumps none notes: 1. terminal pitch is defined by terminal center to center value. 2. outer dimension is defined by center lines between scribe lines. 3. all dimensions in millimeter. 4. marking shown is for package orientation reference only. 5. tolerance is 0.02 unless specified otherwise. 6. all dimensions apply to pbfree (+) package codes only. 7. front - side finish can be either black or clear. basic basic - drawing not to scale - 0.64 0.45 0.19 0.025 0.27 1.20 0.40 2.40 0.20 0.00 w282b3+1 3.20 3.23 2.00 2.03 package outline, 28 bumps wlp pkg. 0.40mm pitch a 21-0627 MAX8973A 9a, three-phase step-down switching regulator www.maximintegrated.com
? 2013 maxim integrated products, inc. 49 revision history revision number revision date description pages changed 0 2/13 initial release maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX8973A 9a, three-phase step-down switching regulator for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

▲Up To Search▲

Price & Availability of MAX8973A

	To Download MAX8973A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .